A resistive memory cell can comprise a two-terminal memory element including an electrolytic tunnel barrier and a mixed valence conductive oxide. U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, now published as U.S. Pub. No. 2006/0171200, and entitled “Memory Using Mixed Valence Conductive Oxides,” is hereby incorporated by reference in its entirety for all purposes and describes non-volatile third dimensional memory elements that can be arranged in a two-terminal, cross-point memory array.
In such a memory cell, a voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier. When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen—PCMO perovskites and lanthanum-nickel-oxygen—LNO perovskites) change valence, their conductivity changes. Additionally, oxygen accumulation in certain electrolytic tunnel barriers (e.g., yttrium stabilized zirconia—YSZ) can also change conductivity. If a portion of the mixed valence conductive oxide near the electrolytic tunnel barrier becomes less conductive, the tunnel barrier width effectively increases. If the electrolytic tunnel barrier becomes less conductive, the tunnel barrier height effectively increases. Both mechanisms can be reversible if the excess oxygen from the electrolytic tunnel barrier flows back into the mixed valence conductive oxide. A memory can be designed to exploit tunnel barrier height modification, tunnel barrier width modification, or both.
The technology allows for the emulation of other memory technologies by duplicating the interface signals and protocols, while accessing the third dimensional memory array. The third dimensional memory array may emulate other types of memory, providing memory combinations within a single component. To illustrate the functionality of a third dimensional memory element, consider that the third dimensional memory element switches to a low resistive state in response to a first write voltage, and switches to a high resistive state when a second write voltage is applied. In some examples, the first write voltage may be opposite in polarity from the second write voltage. The resistance of the memory element may be adjusted by the voltage differential across the memory element. As such, the two terminals of the memory element may be coupled to one or more variable voltage sources to create a voltage differential across the two terminals. For example, a first terminal of the memory element may be programmed to be a certain voltage between, for instance, +3 Volts and −3 Volts. Further, a second terminal of the memory element may be programmed to be another voltage between, for instance, +3 Volts and −3 Volts. In some embodiments, an electrolytic tunnel barrier and one or more mixed valence conductive oxide structures do not need to operate in a silicon substrate, and, therefore, can be fabricated (e.g., back-end-of-the-line BEOL) above circuitry being used for other purposes (e.g., fabricated front-end-of-the-line FEOL). Further, third dimension memory cells in a memory subsystem can be produced with identical or equivalent fabrication processes that produce a logic subsystem. As such, both subsystems can be manufactured in the same or different fabrication plants, or “fabs,” to form processor-memory system as an integrated circuit on a single substrate (e.g., the FEOL portion and BEOL portion comprise a unitary die). For example, this enables a manufacturer to first fabricate a logic subsystem using a CMOS process in a first fab as part of a front-end-of-the-line (FEOL) process, and then port (e.g., transport) a logic subsystem to a second fab at which additional CMOS processing can be used to fabricate multiple memory layers directly on top of logic subsystem as part of a back-end-of-the-line (BEOL) process, whereby the one or more layers of memory are fabricated directly above a substrate (e.g., a silicon wafer) that includes the logic subsystem and its associated circuitry and inter-level interconnect structure (e.g., formed FEOL) for electrically communicating signals between the logic subsystem and the one or more layers of memory. The logic subsystem therefore can be configured to interact with different memory technologies, such as DRAM, SRAM, ROM, and FLASH memories, without fabricating the memory subsystem in a different or a more complex fabrication process than is used to produce logic subsystem. As such, the memory subsystem can be vertically stacked on top of the logic subsystem without an intervening substrate.
Multiple memory layers may be fabricated to arrange the third dimension memory cells in a stacked cross-point array. Stacked cross-point arrays can include memory cells that share conductive array lines with memory cells in other layers as depicted in stacked cross-point array or the conductive array lines in each layer can be electrically isolated (e.g., by a dielectric material such as SiO2 or the like) from the conductive array lines in adjacent memory layers (not shown). That is, two-terminal memory elements can be arranged in a cross-point array (e.g., a two-terminal cross-point memory array) such that one terminal is electrically coupled with an X-direction line and the other terminal is electrically coupled with a Y-direction line and data operations to the two-terminal memory element require a potential difference of sufficient magnitude be applied across the conductive array lines the memory cell is positioned between such the potential difference is applied across the two terminals of the memory element. A stacked cross-point array can include multiple cross-point arrays stacked upon one another, sometimes sharing X-direction and Y-direction lines between layers, and sometimes having isolated lines. Both single-layer cross-point arrays and stacked cross-point arrays can be arranged as third dimension memories.
An array of two-terminal resistive memory cells may be integrated on a silicon wafer. Known schemes for integrating such an array include a vertical arrangement of lines or a planar arrangement of the lines (relative to the substrate). In the vertical arrangement, lines of the array, e.g. bit lines and/or word lines, run perpendicular to the upper surface of the substrate. In the planar arrangement, lines of the array, e.g. bit lines and/or word lines, do not run perpendicular to the upper surface of the substrate.
Known schemes for integrating an array of two-terminal resistive memory cells onto a silicon wafer according to the planar arrangement do not scale well below 20 nm manufacturing and/or are relatively expensive to employ.